The demand for communications systems, such as network, computer, and/or wireless solutions, is constantly increasing. As a result, electronic devices that incorporate integrated circuits (ICs) are continually designed to operate at greater speeds with more efficiency. In a given electronic device, many interconnected ICs are designed to operate and communicate with each other based on very specific timing. As a result, the operation of different components in an electronic device can be synchronized for fast and efficient operation. In addition, as the amount of data that is transferred between two or more integrated circuits increases, data can be organized into data frames, such that data can be transferred in both a serial and parallel manner at higher data rates, such as double-data rate (DDR), triple-data rate, (TDR), or more.
In a high data-rate digital data interface system, a data receiver may require synchronization information from a data transmitter from which the data is provided. For example, the data receiver may require a clock signal to synchronizing timing between the two ends of a data link that interconnects the data transmitter and the data receiver. The data that is transmitted from the data transmitter to the data receiver can be organized into a data frame, such as a data word that is a digital representation of a sample of an analog signal. As such, the data corresponding to the most significant bits (MSBs) and the least significant bits (LSBs) can be ordered by the data receiver to properly reassemble the data.
FIG. 1 illustrates an example of a typical digital data interface system 10. The digital data interface system 10 includes a data transmitter 12 configured to transmit digital data signals to a data receiver 14. The data transmitter 12 can be any of a variety of devices configured to transmit data at a high data rate, such as an analog-to-digital converter (ADC). As another example, the data receiver 14 can be configured to convert digital data transmitted in the digital data signals into analog data, such that the data receiver 14 can be configured as a digital-to-analog converter (DAC). In the example of FIG. 1, the data transmitter 12 provides signals to the data receiver 14 across a plurality of data lines 16. Specifically, the data transmitter 12 provides a clock signal CLK to the data receiver 14, as well as six data signals labeled D0 through D5. Each of the data signals can include consecutive serial data, such that the data that is transmitted from the data transmitter 12 to the data receiver 14 can be organized into data frames, such as data words that are digital representations of respective samples of an analog signal.
FIG. 2 illustrates an example of a timing diagram 50 associated with the digital data interface system 10 of the example of FIG. 1. The timing diagram 50 demonstrates the six digital data signals D0 through D5. The digital data signals D0 through D5 carry bits of a twelve-bit data word 52 having bit numbers B0 through B11, where the bit numbers B0 through B11 are ordered from a lowest ordered LSB to a highest ordered MSB. It is to be understood that, as described herein, the lower-half of the bit numbers of a data word are the LSBs and the upper-half of the bit numbers of a data word are the MSBs. Therefore, in the example of FIG. 2, bits B0 through B5 are the LSBs of the data word 52, with the bit B0 being the lowest ordered LSB, and bits B6 through B11 are the MSBs of the data word 52, with the bit B11 being the highest ordered MSB.
In the example of FIG. 2, the digital data signal D0 includes bits B0 and B1, the digital data signal D1 includes bits B2 and B3, the digital data signal D2 includes bits B4 and B5, the digital data signal D3 includes bits B6 and B7, the digital data signal D4 includes bits B8 and B9, and the digital data signal D5 includes bits B10 and B11. Accordingly, the data word 52 is transmitted in an even/odd manner, such that the even bit numbers of the data word 52 are transmitted first, followed by the odd bit numbers of the data word 52. Thus, in the example of FIG. 2, the digital data signals D0 through D2 carry the LSBs of the data word 52, and the digital data signals D3 through D5 carry the MSBs of the data word 52.
In the example of FIG. 1, the data receiver 14 includes a data decoder 18. Upon the data receiver 14 receiving the clock signal CLK and the data signals D0 through D5, the data decoder 18 latches the data from the data signals D0 through D5 based on the clock signal CLK. In the example of FIG. 2, the data word 52 is transmitted at a DDR. Specifically, at a time T0, the clock signal CLK has a rising-edge, at which time the data decoder 18 latches the even bits B0, B2, B4, B6, B8, and B10. At a time T1, the clock signal CLK has a falling-edge, at which time the data decoder 18 latches the odd bits B1, B3, B5, B7, B9, and B11. Thus, subsequent to the time T1, the data receiver 14 can reorder the latched data bits B0 through B11 from LSB to MSB to properly assemble the data word 52.
FIG. 3 illustrates another example of a timing diagram 100 associated with the digital data interface system 10 of the example of FIG. 1. The timing diagram 100 demonstrates the six digital data signals D0 through D5. The digital data signals D0 through D5 carry bits of a twelve-bit data word 102 having bit numbers B0 through B11, where the bit numbers B0 through B11 are ordered from a lowest ordered LSB to a highest ordered MSB, similar to as described above. Specifically, in the example of FIG. 3, bits B0 through B5 are the LSBs of the data word 102, with the bit B0 being the lowest ordered LSB, and bits B6 through B11 are the MSBs of the data word 102, with the bit B11 being the highest ordered MSB.
In the example of FIG. 3, the digital data signal D0 includes bits B0 and B6, the digital data signal D1 includes bits B1 and B7, the digital data signal D2 includes bits B2 and B8, the digital data signal D3 includes bits B3 and B9, the digital data signal D4 includes bits B4 and B10, the digital data signal D5 includes the B5 and B11. Accordingly, the data word 102 is transmitted in an LSB/MSB manner, such that the LSBs of the data word 102 are transmitted first, followed by the MSBs of the data word 102. Thus, in the example of FIG. 3, the digital data signals D0 through D5 alternate in carrying the LSBs and the MSBs of the data word 102.
Similar to as described above in the example of FIG. 2, the data word 102 in the example of FIG. 3 is transmitted at a DDR. Specifically, at a time T0, the clock signal CLK has a rising-edge, at which time the data decoder 18 latches the LSBs B0 through B5. At a time T1, the clock signal CLK has a falling-edge, at which time the data decoder 18 latches the MSBs B6 through B11. Thus, subsequent to the time T1, the data receiver 14 can reorder the latched data bits B0 through B11 from LSB to MSB to properly assemble the data word 102.
In the example of FIGS. 2 and 3, it is demonstrated that a pin count for a given digital data interface system can be reduced by serializing the data transmitted across each data line. However, in a given data word that is representative of an analog signal sample, the different bits of the data word in a serialized data transmission can include components that affect the performance of the associated DAC or ADC. For example, the LSBs of a given data word can include noise content, such as quantization noise and/or thermal noise, with the lowest ordered LSB including the greatest amount of noise content. In addition, the MSBs of a given data word can include harmonic content of the analog signal, with the highest ordered MSB including the most harmonic content. As such, the harmonic content and noise can distort the analog performance, thus resulting in inaccuracies in the operation of the associated DAC or ADC. Some typical digital data interface systems can reduce noise and/or harmonic content interference by increasing power, but do so at the cost of power efficiency.